The dimensions of semiconductor field effect transistors (FETs) have been steadily shrinking over the last thirty 30 years or so, as scaling to smaller dimensions leads to continuing device performance improvements. Planar FET devices have a conducting gate electrode positioned above a semiconducting channel, and electrically isolated from the channel by a thin layer of gate oxide. Current through the channel is controlled by applying voltage to the conducting gate.
Scaling CMOS technology beyond the 65 nm node is resulting in a conflict between the gate length required for optimum power-limited performance and the gate length required to fit on contacted pitch, with this latter requirement being exceeded by the former design point.
Use of a recessed channel has been proposed but associated with the recessed channel structure is the problem of convex channel corners which have poor transport properties due to geometry-augmented Vt.
That is, as shown in FIG. 1A, which depicts, through a cross-sectional view, a prior art CMOS FET device 10 formed on a heavily doped substrate 12 having a recessed gate electrode (gate conductor) 15 extending from the wafer surface to a depth below the surface, a gate insulator layer 16 surrounding the gate conductor, and, source region 22 and drain region 24 on each side of the recessed gate channel, each convex channel corner 17, 18, such as seen in current devices having such recessed channel structures, results in intrinsically elevated Vt locally at the corner regions of the recessed gate conductor due to electric field non-uniformities (e.g., spreading) from the gate electrode to the channel. This structure degrades device operation and reliability. One prior-art solution to this corner problem is to selectively dope the corners to make them conductive around the corners.
For example, as shown in FIG. 1B, which depicts, through a cross-sectional view, a prior art CMOS FET device 10′ formed on a heavily doped substrate 12 having a recessed gate electrode (gate conductor) 15 extending from the wafer surface to a depth below the surface, a gate insulator layer 16 surrounding the gate conductor, and, source region 22 and drain region 24 on each side of the recessed gate channel, each convex channel corner each corner 17, 18 is “short circuited” with heavy dopant concentrations 27, 28 respectively, in the substrate as known in the art. That is, the doping in the recessed gate corners 17, 18 is intended to ‘short-circuit’ the corners so that, in effect, there were three channels in series, separated by the ‘floating’ intermediate sources at each corner. A high dose ion implant diffusion was applied to the corner regions 17, 18 in the prior art device shown in FIG. 1B, achieving doping concentrations on the order of about 1×1020 cm−3.
However, it is the case that such high-doped corner diffusions degrade the FET devices short channel effects (SCE) and introduce history, even when formed in bulk silicon.
A simpler solution than that discussed in the prior art which better improves suppression of short-channel effects than the prior art would be highly desirable.
Moreover, it is the case that providing long-channel length FETs that physically fit within contacted pitch has been shown to benefit performance. Thus, it would further be desirable to provide a novel FET device structure and method of manufacture whereby the device gate is recessed, however, does not result in the undesirable short channel effects (SCE); and further, to making long-channel length FETs that physically fit within contacted pitch to benefit performance.